With miniaturization high integration of a semiconductor device, variations in threshold voltage of a transistor caused by statistical fluctuations of channel impurities become obvious. The threshold voltage is one of the important parameters to determine the performance of a transistor, and for manufacturing a high-performance and highly reliable semiconductor device, it is important to reduce the variations in threshold voltage caused by statistical fluctuations of impurities.
As one of the techniques to reduce variations in threshold voltage caused by statistical fluctuations of impurities, a transistor structure called a DCC transistor (Deeply Depleted Channel transistor) has been proposed. The DDC transistor is one in which a non-doped epitaxial silicon layer is formed on a high-concentration channel impurity layer having a steep impurity concentration distribution.
On the other hand, a logic semiconductor device having a nonvolatile semiconductor memory mixedly mounted thereon creates product fields such as CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array), and results in creating a large market thanks to its programmable characteristic.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2001-274154
[Parent Document 2] Japanese Laid-open Patent Publication No. 2004-165157
[Patent Document 3] Japanese Laid-open Patent Publication No. 2005-005516
[Patent Document 4] Japanese Translation of PCT Application No. 2009-510769
[Non-Patent Document 1] Ming-Yi Lee et al., “Anomalous Single Bit Retention Induced by Asymmetric STI-Corner-Thinning for Floating Gate Flash Memories”, Proc. of Physical and Failure Analysis of Integrated Circuits, pp. 263-267, 2012
[Non-Patent Document 2] A. Chimenton et al., “Drain-accelerated Degradation of Tunnel Oxides in Flash memories”, IEEE IEDM Tech. Dig., pp. 167-170, 2002
[Non-Patent Document 3] G. Ghidini, “Charge-related Phenomena and Reliability of Non-volatile Memories”, Microelectronics Reliability Vol. 52, pp. 1876-1882, 2012
From now, it is also expected that a semiconductor device having a DDC transistor and a nonvolatile memory transistor mixedly mounted thereon is demanded. However, the DDC transistor and the nonvolatile memory transistor each have a unique manufacturing process, and the simple combination of both the processes makes it impossible to mixedly mount the transistors without deteriorating properties of these transistors.